1. Field of the Invention
The present invention relates to solid state photosensitive devices, more particularly solid state photosensitive devices for infrared operation.
2. Description of the Prior Art
The photosensitive devices used at present are formed mainly by N photodetectors connected through a transition zone to a multiplexer preferably formed by a charge transfer shift register with N parallel inputs and a series output. More specifically and, as shown in FIGS. 1 and 2a which are respectively a cross sectional view and a top view of a photosensitive device of the prior art formed mainly by a hybrid circuit, namely a circuit in which the photodetectors are formed on a first substrate whereas the transition zone and the shift register are formed on a second substrate 2, the photodetectors used are photodiodes 1 whose anode A receives a biassing voltage V.sub.SD whereas the cathode K is connected by a connection to the charge integration zone. The charge integration zone comprises a readout diode D formed by a diffusion of a type opposite that of substrate 2. This diode D is connected by connection 3 to the cathode K of the photodiode 1. A control gate G.sub.C separates each diode D from a charge storage capacity C formed by a gate G.sub.ST, an insulating layer and the substrate. In the Figures, for the sake of clarity, the layer of insulation which separates the different gates from the surface of the semiconductor substrate 2 has not been shown. A transfer gate G.sub.T separates each capacity C from a stage G.sub.CCD of the charge transfer shift register R having parallel inputs and a series output.
However a charge transfer shift register has the disadvantage of offering only a limited storage possibility, which consequently limits the maximum charge which may be transferred from the storage capacities into said register.
This is particularly troublesome in the case of infrared. In fact, in this case temperature variations are read out and the useful information is superimposed on a background charge which may be relatively high but which is of no interest from the point of view of the signal.
Consequently, it has been proposed to eliminate at least a part of this background charge before transferring it into the shift register. For this base-clipping, as shown in FIG. 2a , on the side of each storage gate G.sub.ST there is provided a gate G.sub.R and a diffusion D.sub.R of a type opposite that of the substrate connected to a reset voltage V.sub.R. The gate G.sub.R is controlled by a potential which is brought to a high level once the charges have been transferred into the shift register, so as to level again the corresponding storage capacity.
The operation of this device will now be explained with reference to FIG. 2b which shows the surface potentials of the different elements of FIG. 2 in substrate 2. During integration, the photoelectrons e.sup.- delivered by the photodiode are stored under the storage gate G.sub.ST. During this charge integration period, the relevelling MOS T transistor whose induced source is formed by the storage capacity, whose gate is formed by gate G.sub.R and drain by diffusion D.sub.R, is disabled, that is to say that gate G.sub.R is at a low level. At the end of the integration time, a charge amount Q is obtained under the storage gate G.sub.ST. This charge Q may be expressed in the form Q.sub.0 +Q.sub.1 in which Q.sub.0 designates the part of the background charge or pedestal which may be eliminated. Then the potential barrier under the transfer gate G.sub.T is lowered to the level V.sub.1 shown with a broken line in FIG. 2b so that the charge Q.sub.1 is transferred under the stage G.sub.CCD of the shift register. Then the potential barrier under G.sub.R is brought to a high level by increasing the biassing voltage of this gate so as to enable the relevelling MOS T transistor, which allows the charge Q.sub.0 to be removed towards the reset voltage V.sub.R. The potential barriers under gates G.sub.R and G.sub.T are brought to a low level and a new charge integration begins.
This base clipping process has the main drawback of requiring a gate G.sub.R and a diffusion D.sub.R for each photodiode--multiplexer coupling point as well as additional connections for biassing these two elements. This causes an increase of the surface of the readout circuit. Another disadvantage of this base clipping process resides in the control electronics which must comprise two additional voltages and in the connections which comprise two additional wires.
Consequently, the aim of the present invention is to propose a new base clipping process which allows the same function to be obtained without complicating the structure of the solid state photosensitive device.